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| author |   Fabrizio Castro <fabrizio.castro.jz@renesas.com> | 2023-06-22 12:33:39 +0100 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2023-06-23 11:04:20 +0100 |
| commit | 83c624d8842d7f6c0780bc7658cb8fa67c0501f1 (patch) | |
| tree | a2c243ba6dca4fd6776c490828c064aa131dd2f3 /scripts/generate_rust_analyzer.py | |
| parent | spi: dt-bindings: Add bindings for RZ/V2M CSI (diff) | |
| download | wireguard-linux-83c624d8842d7f6c0780bc7658cb8fa67c0501f1.tar.xz wireguard-linux-83c624d8842d7f6c0780bc7658cb8fa67c0501f1.zip | |
spi: Add support for Renesas CSI
The RZ/V2M SoC comes with the Clocked Serial Interface (CSI)
IP, which is a master/slave SPI controller.
This commit adds a driver to support CSI master mode.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/Message-Id: <20230622113341.657842-4-fabrizio.castro.jz@renesas.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions