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| author |   Lingyu Liu <lingyu.liu@intel.com> | 2023-03-28 10:49:11 +0000 |
|---|---|---|
| committer |   Tony Nguyen <anthony.l.nguyen@intel.com> | 2023-04-04 08:34:52 -0700 |
| commit | 83c911dc5e0e8e6eaa6431c06972a8f159bfe2fc (patch) | |
| tree | fefa2a6a1e7cb4fcf4f8a834b94c13ca9279ef22 /scripts/generate_rust_analyzer.py | |
| parent | ice: fix wrong fallback logic for FDIR (diff) | |
| download | wireguard-linux-83c911dc5e0e8e6eaa6431c06972a8f159bfe2fc.tar.xz wireguard-linux-83c911dc5e0e8e6eaa6431c06972a8f159bfe2fc.zip | |
ice: Reset FDIR counter in FDIR init stage
Reset the FDIR counters when FDIR inits. Without this patch,
when VF initializes or resets, all the FDIR counters are not
cleaned, which may cause unexpected behaviors for future FDIR
rule create (e.g., rule conflict).
Fixes: 1f7ea1cd6a37 ("ice: Enable FDIR Configure for AVF")
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Lingyu Liu <lingyu.liu@intel.com>
Tested-by: Rafal Romanowski <rafal.romanowski@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions