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| author |   Heiko Stuebner <heiko@sntech.de> | 2025-05-03 22:25:30 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2025-05-08 20:29:02 +0200 |
| commit | 897adaf536ab01f130ce0b53a635a592733c0f24 (patch) | |
| tree | 8098f4c0bcaf976e8e0b252e8eb417eb605dad24 /scripts/generate_rust_analyzer.py | |
| parent | dt-bindings: clock: rk3036: add SCLK_USB480M clock-id (diff) | |
| download | wireguard-linux-897adaf536ab01f130ce0b53a635a592733c0f24.tar.xz wireguard-linux-897adaf536ab01f130ce0b53a635a592733c0f24.zip | |
clk: rockchip: rk3036: fix implementation of usb480m clock mux
Contrary to how it is implemented right now, this mux is controllable via
a bit in CRU_MUSC_CON (same bit as on rk3128 even) and allows switching
between xin24m and the 480m output of the usb2phy.
So drop the hard-coded fixed-factor clock and implement the correct mux
instead.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250503202532.992033-3-heiko@sntech.de
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions