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| author |   Lukas Bulwahn <lukas.bulwahn@gmail.com> | 2023-01-11 11:05:54 +0100 |
|---|---|---|
| committer |   Marc Zyngier <maz@kernel.org> | 2023-02-05 11:19:03 +0000 |
| commit | 9c1a7bfc2993112cfb3056b18301fcafe5c2fde5 (patch) | |
| tree | eea5cfa7c1828dc82c834ba4f0e90af7a08b3c06 /scripts/generate_rust_analyzer.py | |
| parent | irqchip/loongson-liointc: Save/restore int_edge/int_pol registers during S3/S4 (diff) | |
| download | wireguard-linux-9c1a7bfc2993112cfb3056b18301fcafe5c2fde5.tar.xz wireguard-linux-9c1a7bfc2993112cfb3056b18301fcafe5c2fde5.zip | |
irqchip/ls-scfg-msi: Simplify Kconfig dependencies
Having both PCI_MSI and PCI is redundant. Drop PCI.
Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
[maz: cut commit message extra verbosity]
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20230111100554.24500-1-lukas.bulwahn@gmail.com
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions