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| author |   Mika Westerberg <mika.westerberg@linux.intel.com> | 2023-03-03 11:25:08 +0200 |
|---|---|---|
| committer | Mika Westerberg <mika.westerberg@linux.intel.com> | 2023-03-13 11:54:14 +0200 |
| commit | acec726473822bc6b585961f4ca2a11fa7f28341 (patch) | |
| tree | 36110339c54c020e75f997b722f15d82cbbfe9f7 /scripts/generate_rust_analyzer.py | |
| parent | thunderbolt: Add quirk to disable CLx (diff) | |
| download | wireguard-linux-acec726473822bc6b585961f4ca2a11fa7f28341.tar.xz wireguard-linux-acec726473822bc6b585961f4ca2a11fa7f28341.zip | |
thunderbolt: Fix memory leak in margining
Memory for the usb4->margining needs to be relased for the upstream port
of the router as well, even though the debugfs directory gets released
with the router device removal. Fix this.
Fixes: d0f1e0c2a699 ("thunderbolt: Add support for receiver lane margining")
Cc: stable@vger.kernel.org
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions