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| author |   Emil Renner Berthing <kernel@esmil.dk> | 2023-04-01 19:19:25 +0800 |
|---|---|---|
| committer |   Conor Dooley <conor.dooley@microchip.com> | 2023-04-05 15:44:12 +0100 |
| commit | edab7204afe55bdf2d17d3490eb88497ba60f628 (patch) | |
| tree | 99489ce579d1af3d00551fc078b6949d0a99b59a /scripts/generate_rust_analyzer.py | |
| parent | reset: starfive: jh71x0: Use 32bit I/O on 32bit registers (diff) | |
| download | wireguard-linux-edab7204afe55bdf2d17d3490eb88497ba60f628.tar.xz wireguard-linux-edab7204afe55bdf2d17d3490eb88497ba60f628.zip | |
clk: starfive: Add StarFive JH7110 system clock driver
Add driver for the StarFive JH7110 system clock controller and
register an auxiliary device for system reset controller which
is named as "rst-sys".
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions