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| author |   Hersen Wu <hersenxs.wu@amd.com> | 2023-03-09 15:58:54 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2023-03-23 09:39:34 -0400 |
| commit | f9537b1fa7fb51c2162bc15ce469cbbf1ca0fbfe (patch) | |
| tree | 072e6d6f61b4a6eba241177970e7e64c194696ca /scripts/generate_rust_analyzer.py | |
| parent | drm/amd/display: fix wrong index used in dccg32_set_dpstreamclk (diff) | |
| download | wireguard-linux-f9537b1fa7fb51c2162bc15ce469cbbf1ca0fbfe.tar.xz wireguard-linux-f9537b1fa7fb51c2162bc15ce469cbbf1ca0fbfe.zip | |
drm/amd/display: Set dcn32 caps.seamless_odm
[Why & How]
seamless_odm set was not picked up while
merging commit 2d017189e2b3 ("drm/amd/display:
Blank eDP on enable drv if odm enabled")
Fixes: 2d017189e2b3 ("drm/amd/display: Blank eDP on enable drv if odm enabled")
Reviewed-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions