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| author |   Adrian Hunter <adrian.hunter@intel.com> | 2024-11-01 11:50:31 -0700 |
|---|---|---|
| committer |   Sean Christopherson <seanjc@google.com> | 2024-12-19 07:34:10 -0800 |
| commit | fdd2db5126ce9cce22947354008d430252b08a03 (patch) | |
| tree | 01ad373becff4930167a3bd0ffee06191b024a2d /scripts/generate_rust_analyzer.py | |
| parent | KVM: nVMX: Defer SVI update to vmcs01 on EOI when L2 is active w/o VID (diff) | |
| download | wireguard-linux-fdd2db5126ce9cce22947354008d430252b08a03.tar.xz wireguard-linux-fdd2db5126ce9cce22947354008d430252b08a03.zip | |
KVM: VMX: Allow toggling bits in MSR_IA32_RTIT_CTL when enable bit is cleared
Allow toggling other bits in MSR_IA32_RTIT_CTL if the enable bit is being
cleared, the existing logic simply ignores the enable bit. E.g. KVM will
incorrectly reject a write of '0' to stop tracing.
Fixes: bf8c55d8dc09 ("KVM: x86: Implement Intel PT MSRs read/write emulation")
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
[sean: rework changelog, drop stable@]
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Link: https://lore.kernel.org/r/20241101185031.1799556-3-seanjc@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions