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| author |   Helge Deller <deller@gmx.de> | 2023-11-20 15:39:03 +0100 |
|---|---|---|
| committer | Helge Deller <deller@gmx.de> | 2023-11-25 09:43:17 +0100 |
| commit | a80aeb86542a50aa8521729ea4cc731ee7174f03 (patch) | |
| tree | 988c7ca64dc36db23728124d145c006c730e6aaf /scripts/generate_rust_target.rs | |
| parent | parisc: Mark ex_table entries 32-bit aligned in assembly.h (diff) | |
| download | wireguard-linux-a80aeb86542a50aa8521729ea4cc731ee7174f03.tar.xz wireguard-linux-a80aeb86542a50aa8521729ea4cc731ee7174f03.zip | |
parisc: Mark ex_table entries 32-bit aligned in uaccess.h
Add an align statement to tell the linker that all ex_table entries and as
such the whole ex_table section should be 32-bit aligned in vmlinux and modules.
Signed-off-by: Helge Deller <deller@gmx.de>
Cc: stable@vger.kernel.org # v6.0+
Diffstat (limited to 'scripts/generate_rust_target.rs')
0 files changed, 0 insertions, 0 deletions