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| author |   Xingyu Wu <xingyu.wu@starfivetech.com> | 2023-07-17 10:30:38 +0800 |
|---|---|---|
| committer |   Conor Dooley <conor.dooley@microchip.com> | 2023-07-19 18:08:00 +0100 |
| commit | a013e9818734ade52944e73f64242633c6cd4128 (patch) | |
| tree | ec1fe654fdbaaf0b64b0c2a3d31b88ef369cd1c0 /scripts/rust_is_available_test.py | |
| parent | clk: starfive: Add StarFive JH7110 PLL clock driver (diff) | |
| download | wireguard-linux-a013e9818734ade52944e73f64242633c6cd4128.tar.xz wireguard-linux-a013e9818734ade52944e73f64242633c6cd4128.zip | |
clk: starfive: jh7110-sys: Add PLL clocks source from DTS
Modify PLL clocks source to be got from DTS or
the fixed factor clocks.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions