diff options
| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2026-04-13 19:24:51 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2026-04-27 11:18:04 +0200 |
| commit | c88ab9407986836820848128ce1f90f2fa49da95 (patch) | |
| tree | 7e3f1a929f7f017765dec63962f9b0abf2fe5784 /security/apparmor/ssh:/git@git.zx2c4.com/git:/git.zx2c4.com | |
| parent | pinctrl: renesas: rzg2l: Fix incorrect PUPD register offset for high pins during suspend/resume (diff) | |
pinctrl: renesas: rzg2l: Fix SMT register cache handling
Store SMT register cache per bank instead of using a single array.
On RZ/V2H(P), RZ/V2N, and RZ/G3E, the SMT register is split across two
32-bit registers: bits 0/8/16/24 control pins 0-3, while pins 4-7 are
controlled by the corresponding bits in the next register. The previous
implementation cached only a single SMT register, leading to incomplete
save/restore of SMT state.
Convert cache->smt to a per-bank array and allocate storage for both
halves. Update suspend/resume handling to save and restore both SMT
registers when present.
Fixes: 837afa592c623 ("pinctrl: renesas: rzg2l: Add suspend/resume support for Schmitt control registers")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260413182456.811543-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'security/apparmor/ssh:/git@git.zx2c4.com/git:/git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions