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| author |   Alex Wilson <alex.david.wilson@gmail.com> | 2015-07-17 20:23:55 -0600 |
|---|---|---|
| committer |   Michal Simek <michal.simek@xilinx.com> | 2015-07-31 10:50:05 +0200 |
| commit | 6de663fe33b35fc95e751f907aa28e608c38f121 (patch) | |
| tree | 0f7a95287fda0acd70d22a461b529f6707d37c10 /tools/perf/scripts/python/call-graph-from-postgresql.py | |
| parent | Documentation: devicetree: Add ECC information to synopsys ddr controller (diff) | |
| download | wireguard-linux-6de663fe33b35fc95e751f907aa28e608c38f121.tar.xz wireguard-linux-6de663fe33b35fc95e751f907aa28e608c38f121.zip | |
ARM: zynq: DT: Add missing interrupt for L2 pl310
Add pl310 interrupt to the Zynq devicetree.
Signed-off-by: Alex Wilson <alex.david.wilson@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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0 files changed, 0 insertions, 0 deletions