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| author |   Marek Szyprowski <m.szyprowski@samsung.com> | 2015-01-08 07:49:41 +0100 |
|---|---|---|
| committer |   Russell King <rmk+kernel@arm.linux.org.uk> | 2015-01-16 14:35:26 +0000 |
| commit | 00218241aa0846e75d31b1dbadb5f8a76be1cc97 (patch) | |
| tree | 98c70e0fe37d7f06e8d68ef47893004c271c4938 /tools/perf/scripts/python/call-graph-from-postgresql.py | |
| parent | ARM: 8257/1: OMAP2+: use common l2cache initialization code (diff) | |
| download | wireguard-linux-00218241aa0846e75d31b1dbadb5f8a76be1cc97.tar.xz wireguard-linux-00218241aa0846e75d31b1dbadb5f8a76be1cc97.zip | |
ARM: 8258/1: l2c: use l2c_write_sec() for restoring latency and filter regs
All four register for latency and filter settings cannot be written in
non-secure mode and they should go through l2c_write_sec(). More on this
can be found in CoreLink Level 2 Cache Controller L2C-310 Technical
Reference Manual, 3.2. Register summary, table 3.1. This have been checked
the TRM for r3p3, but it should be uniform for all revisions.
Reported-by: Nishanth Menon <nm@ti.com>
Suggested-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'tools/perf/scripts/python/call-graph-from-postgresql.py')
0 files changed, 0 insertions, 0 deletions