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authorDave Airlie <airlied@redhat.com>2015-09-04 13:09:20 +1000
committerDave Airlie <airlied@redhat.com>2015-09-04 13:09:20 +1000
commit5b78cb668764061bd8a06f73f9bd081ba6942fef (patch)
treeec2c05f75d4cb3d5a667bf0bde7d623db2f84d40 /tools/perf/scripts/python/call-graph-from-postgresql.py
parentMerge branch 'drm-rockchip-2015-08-26' of https://github.com/markyzq/kernel-drm-rockchip into drm-next (diff)
parenti915: Set ddi_pll_sel in DP MST path (diff)
downloadwireguard-linux-5b78cb668764061bd8a06f73f9bd081ba6942fef.tar.xz
wireguard-linux-5b78cb668764061bd8a06f73f9bd081ba6942fef.zip
Merge tag 'drm-intel-next-fixes-2015-09-02' of git://anongit.freedesktop.org/drm-intel into drm-next
i915 display fixes headed for v4.3. Mostly SKL, but some regression fixes too. * tag 'drm-intel-next-fixes-2015-09-02' of git://anongit.freedesktop.org/drm-intel: i915: Set ddi_pll_sel in DP MST path drm/i915: Don't use link_bw for PLL setup drm/i915: Preserve SSC earlier drm/i915/skl: Adding DDI_E power well domain drm/i915: eDP can be present on DDI-E drm/i915/skl: Enable DDI-E drm/i915: Enable HDMI on DDI-E drm/i915: apply the PCI_D0/D3 hibernation workaround everywhere on pre GEN6 drm/i915: Check DP link status on long hpd too drm/i915: set CDCLK if DPLL0 enabled during resuming from S3
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