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| author |   Hai Li <hali@codeaurora.org> | 2015-06-26 16:03:26 -0400 |
|---|---|---|
| committer |   Rob Clark <robdclark@gmail.com> | 2015-08-15 18:27:16 -0400 |
| commit | b96b3a06d1211ba86674db99a6aafe39ef4cbed2 (patch) | |
| tree | b1bce7da9c4ae8e0ec8d8cd0ef4be3cb55cb343d /tools/perf/scripts/python/call-graph-from-postgresql.py | |
| parent | drm/msm/mdp5: Allocate CTL for each display interface (diff) | |
| download | wireguard-linux-b96b3a06d1211ba86674db99a6aafe39ef4cbed2.tar.xz wireguard-linux-b96b3a06d1211ba86674db99a6aafe39ef4cbed2.zip | |
drm/msm/mdp5: Allocate CTL0/1 for dual DSI single FLUSH
This change takes advantage of a HW feature that synchronize
flush operation on CTL1 to CTL0, to keep dual DSI pipes in
sync.
Signed-off-by: Hai Li <hali@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'tools/perf/scripts/python/call-graph-from-postgresql.py')
0 files changed, 0 insertions, 0 deletions