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| author |   Uma Shankar <uma.shankar@intel.com> | 2016-02-18 13:49:26 +0200 |
|---|---|---|
| committer |   Jani Nikula <jani.nikula@intel.com> | 2016-02-18 19:06:32 +0200 |
| commit | d6e3af5498390ae58b03b515ad0eb92520a8ad6b (patch) | |
| tree | be37f8226a4b1cad81c6554658c43ff569219288 /tools/perf/scripts/python/call-graph-from-postgresql.py | |
| parent | drm/i915/skl: Ensure HW is powered during DDB HW state readout (diff) | |
| download | wireguard-linux-d6e3af5498390ae58b03b515ad0eb92520a8ad6b.tar.xz wireguard-linux-d6e3af5498390ae58b03b515ad0eb92520a8ad6b.zip | |
drm/i915/bxt: Remove DSP CLK_GATE programming for BXT
DSP CLK_GATE registers are specific to BYT and CHT.
Avoid programming the same for BXT platform.
v2: Rebased on latest drm nightly branch.
v3: Fixed Jani's review comments
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1455796166-13052-1-git-send-email-jani.nikula@intel.com
Diffstat (limited to 'tools/perf/scripts/python/call-graph-from-postgresql.py')
0 files changed, 0 insertions, 0 deletions