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| author |   Bard Liao <bardliao@realtek.com> | 2017-07-20 13:07:50 +0800 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2017-07-20 13:21:28 +0100 |
| commit | 01dfb1ec15ce6120055401953265c7b51e899292 (patch) | |
| tree | 6593d04d8dd2c4c71ef97b0d912e73370720445d /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ASoC: rt5665: force using PLL if MCLK is not suitable (diff) | |
| download | wireguard-linux-01dfb1ec15ce6120055401953265c7b51e899292.tar.xz wireguard-linux-01dfb1ec15ce6120055401953265c7b51e899292.zip | |
ASoC: rt5665: add clcok control for master mode
Add i2s clock control for codec master mode.
Signed-off-by: Bard Liao <bardliao@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions