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| author |   Apurva Nandan <a-nandan@ti.com> | 2021-07-16 23:25:03 +0000 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2021-08-05 20:18:10 +0100 |
| commit | 0395be967b067d99494113d78470574e86a02ed4 (patch) | |
| tree | 09a1efe48dddc022497cc63044668ef156ed1511 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | spi: mediatek: Fix fifo transfer (diff) | |
| download | wireguard-linux-0395be967b067d99494113d78470574e86a02ed4.tar.xz wireguard-linux-0395be967b067d99494113d78470574e86a02ed4.zip | |
spi: cadence-quadspi: Fix check condition for DTR ops
buswidth and dtr fields in spi_mem_op are only valid when the
corresponding spi_mem_op phase has a non-zero length. For example,
SPI NAND core doesn't set buswidth when using SPI_MEM_OP_NO_ADDR
phase.
Fix the dtr checks in set_protocol() and suppports_mem_op() to
ignore empty spi_mem_op phases, as checking for dtr field in
empty phase will result in false negatives.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Link: https://lore.kernel.org/r/20210716232504.182-3-a-nandan@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions