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| author |   Sung Lee <sung.lee@amd.com> | 2019-12-19 11:37:49 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-01-16 14:15:35 -0500 |
| commit | 08f6c859211cc0af1b32e7fa7ec583699a06d6c3 (patch) | |
| tree | 55772c67ded3b643ff3e4667a13384722ffa2e62 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/amd/display: rename _lvp to l_vp (diff) | |
| download | wireguard-linux-08f6c859211cc0af1b32e7fa7ec583699a06d6c3.tar.xz wireguard-linux-08f6c859211cc0af1b32e7fa7ec583699a06d6c3.zip | |
drm/amd/display: Use SMU ClockTable Values for DML Calculations
[Why]
DML Initialization was previously done on dcn21_resource initialization.
This meant that DML soc struct was populated with hardcoded values.
[How]
Move DML initialization to after updating bounding box, to use clock table
values from SMU.
Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions