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| author |   Daniel Palmer <daniel@0x0f.com> | 2020-07-10 18:45:39 +0900 |
|---|---|---|
| committer |   Arnd Bergmann <arnd@arndb.de> | 2020-07-28 11:13:49 +0200 |
| commit | 09220c579c7873a89a07f4f55da9662b1b95355f (patch) | |
| tree | 5d196fc89dc8b0cb57ab40078f4951d0f18acc1c /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: mstar: Add machine for MStar/Sigmastar Armv7 SoCs (diff) | |
| download | wireguard-linux-09220c579c7873a89a07f4f55da9662b1b95355f.tar.xz wireguard-linux-09220c579c7873a89a07f4f55da9662b1b95355f.zip | |
ARM: mstar: Add binding details for mstar,l3bridge
This adds a YAML description of the l3bridge node needed by the
platform code for the MStar/SigmaStar Armv7 SoCs.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions