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| author |   Tanmay Jagdale <tanmay@marvell.com> | 2021-09-01 18:40:48 +0530 |
|---|---|---|
| committer |   Mathieu Poirier <mathieu.poirier@linaro.org> | 2021-10-27 11:44:32 -0600 |
| commit | 0ab47f8079f27edc44ea0bcc67078561bcfdf542 (patch) | |
| tree | 3ce4a8c466a2e2e62ba43d5d9649d682e945b2e1 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | coresight: cpu-debug: Control default behavior via Kconfig (diff) | |
| download | wireguard-linux-0ab47f8079f27edc44ea0bcc67078561bcfdf542.tar.xz wireguard-linux-0ab47f8079f27edc44ea0bcc67078561bcfdf542.zip | |
dt-bindings: coresight: Add burst size for TMC
Add "arm,max-burst-size" optional property for TMC ETR.
If specified, this value indicates the maximum burst size
that can be initiated by TMC on the AXI bus.
Signed-off-by: Tanmay Jagdale <tanmay@marvell.com>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210901131049.1365367-2-tanmay@marvell.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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