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| author |   George Shen <George.Shen@amd.com> | 2021-12-08 20:28:14 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2021-12-30 08:54:44 -0500 |
| commit | 0d988e5de7aa5ee8865cbc664180ae67918a6b19 (patch) | |
| tree | 52a49a9a6bcd9798afa109a12a19057fae1adebf /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/amd/display: Send s0i2_rdy in stream_count == 0 optimization (diff) | |
| download | wireguard-linux-0d988e5de7aa5ee8865cbc664180ae67918a6b19.tar.xz wireguard-linux-0d988e5de7aa5ee8865cbc664180ae67918a6b19.zip | |
drm/amd/display: Remove CR AUX RD Interval limit for LTTPR
[Why]
DP spec specifies that DPRX shall use the read interval in the
TRAINING_AUX_RD_INTERVAL_PHY_REPEATER LTTPR DPCD register. This
register's bit definition is the same as the AUX read interval register
for DPRX.
[How}
Remove logic which forces AUX read interval to 100us for repeaters when
in LTTPR non-transparent mode.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Wesley Chalmers <wesley.chalmers@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: George Shen <George.Shen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions