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| author |   José Roberto de Souza <jose.souza@intel.com> | 2021-05-14 08:37:10 -0700 |
|---|---|---|
| committer |   Matt Roper <matthew.d.roper@intel.com> | 2021-05-14 19:48:38 -0700 |
| commit | 2680bea758f270c11f8a5b78152930b92596f2ef (patch) | |
| tree | eeeec716d046f7c08e99139c897cf613403e383a /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915/adl_p: Implement Wa_22011091694 (diff) | |
| download | wireguard-linux-2680bea758f270c11f8a5b78152930b92596f2ef.tar.xz wireguard-linux-2680bea758f270c11f8a5b78152930b92596f2ef.zip | |
drm/i915/display/adl_p: Implement Wa_22011320316
Implementation details are in the HSD 22011320316, requiring CD clock
to be at least 307MHz to make DC states to work.
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-19-matthew.d.roper@intel.com
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