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| author |   Lars Povlsen <lars.povlsen@microchip.com> | 2020-06-15 15:32:39 +0200 |
|---|---|---|
| committer |   Arnd Bergmann <arnd@arndb.de> | 2020-07-22 22:28:45 +0200 |
| commit | 39c8378a1cdf856a3671b6431f99352b75a07248 (patch) | |
| tree | 27368243f736411ed54c0edbbeddfc455ca4cf3f /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | dt-bindings: clock: sparx5: Add Sparx5 SoC DPLL clock (diff) | |
| download | wireguard-linux-39c8378a1cdf856a3671b6431f99352b75a07248.tar.xz wireguard-linux-39c8378a1cdf856a3671b6431f99352b75a07248.zip | |
dt-bindings: clock: sparx5: Add bindings include file
The Sparx5 support 9 different clock outputs. This include file has
defines for each supported clock ordinal.
Link: https://lore.kernel.org/r/20200615133242.24911-8-lars.povlsen@microchip.com
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions