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| author |   Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2019-09-21 17:04:11 +0200 |
|---|---|---|
| committer |   Jerome Brunet <jbrunet@baylibre.com> | 2019-10-01 14:46:30 +0200 |
| commit | 44b09b11b813b8550e6b976ea51593bc23bba8d1 (patch) | |
| tree | af2503e988d13db4978beaa3a9533d8d41eabcb5 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Linux 5.4-rc1 (diff) | |
| download | wireguard-linux-44b09b11b813b8550e6b976ea51593bc23bba8d1.tar.xz wireguard-linux-44b09b11b813b8550e6b976ea51593bc23bba8d1.zip | |
clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate
The meson-saradc driver manually sets the input clock for
sar_adc_clk_sel. Update the GXBB clock driver (which is used on GXBB,
GXL and GXM) so the rate settings on sar_adc_clk_div are propagated up
to sar_adc_clk_sel which will let the common clock framework select the
best matching parent clock if we want that.
This makes sar_adc_clk_div consistent with the axg-aoclk and g12a-aoclk
drivers, which both also specify CLK_SET_RATE_PARENT.
Fixes: 33d0fcdfe0e870 ("clk: gxbb: add the SAR ADC clocks and expose them")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions