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| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2017-09-01 17:31:21 +0300 |
|---|---|---|
| committer |   Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-09-01 10:30:37 -0700 |
| commit | 54706fa973b592eb8b3a6e04ac888d5fbb704d0a (patch) | |
| tree | 264970de19ef38d3d948c3b550e88cad19a09a5c /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915/edp: Increase T12 panel delay to 900 ms to fix DP AUX CH timeouts (diff) | |
| download | wireguard-linux-54706fa973b592eb8b3a6e04ac888d5fbb704d0a.tar.xz wireguard-linux-54706fa973b592eb8b3a6e04ac888d5fbb704d0a.zip | |
drm/i915: Make i9xx_load_ycbcr_conversion_matrix() static
Make i9xx_load_ycbcr_conversion_matrix() static to appease sparse:
intel_color.c:110:6: warning: symbol 'i9xx_load_ycbcr_conversion_matrix' was not declared. Should it be static?
Cc: Shashank Sharma <shashank.sharma@intel.com>
Fixes: 25edf91501b8 ("drm/i915: prepare csc unit for YCBCR420 output")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170901143123.7590-1-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
(cherry picked from commit 0abd9976960a5c46b5cc49f2f53281774a8a4a3e)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions