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authorClaudiu Beznea <claudiu.beznea@microchip.com>2020-06-10 12:05:36 +0300
committerAlexandre Belloni <alexandre.belloni@bootlin.com>2020-06-26 22:40:22 +0200
commit5f6b33f463468b9595eebfed142756ba13ea2b60 (patch)
tree297040d65655cfc2a555e41c0a142c9c4ec2b668 /tools/perf/scripts/python/export-to-postgresql.py
parentdt-bindings: rtc: add microchip,sam9x60-rtt (diff)
downloadwireguard-linux-5f6b33f463468b9595eebfed142756ba13ea2b60.tar.xz
wireguard-linux-5f6b33f463468b9595eebfed142756ba13ea2b60.zip
ARM: dts: sam9x60: add rtt
Add RTT. Allong with it enable GBPR as it is requested by RTT. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1591779936-18577-4-git-send-email-claudiu.beznea@microchip.com
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