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| author |   Zhenyu Ye <yezhenyu2@huawei.com> | 2020-07-10 17:41:58 +0800 |
|---|---|---|
| committer |   Catalin Marinas <catalin.marinas@arm.com> | 2020-07-10 16:27:49 +0100 |
| commit | 61c11656b67b0a30f702f240aabe81fd93e702ac (patch) | |
| tree | 827c14c8caabbf4c8fb54982d9a23cd81aff96f3 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: Shift the __tlbi_level() indentation left (diff) | |
| download | wireguard-linux-61c11656b67b0a30f702f240aabe81fd93e702ac.tar.xz wireguard-linux-61c11656b67b0a30f702f240aabe81fd93e702ac.zip | |
arm64: tlb: don't set the ttl value in flush_tlb_page_nosync
flush_tlb_page_nosync() may be called from pmd level, so we
can not set the ttl = 3 here.
The callstack is as follows:
pmdp_set_access_flags
ptep_set_access_flags
flush_tlb_fix_spurious_fault
flush_tlb_page
flush_tlb_page_nosync
Fixes: e735b98a5fe0 ("arm64: Add tlbi_user_level TLB invalidation helper")
Reported-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
Link: https://lore.kernel.org/r/20200710094158.468-1-yezhenyu2@huawei.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions