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| author |   Chunfeng Yun <chunfeng.yun@mediatek.com> | 2020-02-11 11:21:13 +0800 |
|---|---|---|
| committer |   Kishon Vijay Abraham I <kishon@ti.com> | 2020-03-20 19:34:29 +0530 |
| commit | 657a9edec0757cc6841672fda8065b2338c6b073 (patch) | |
| tree | 01a6fb34cf07770b57a57300cca868d1fd17d16a /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | phy: phy-mtk-tphy: add a property for internal resistance (diff) | |
| download | wireguard-linux-657a9edec0757cc6841672fda8065b2338c6b073.tar.xz wireguard-linux-657a9edec0757cc6841672fda8065b2338c6b073.zip | |
phy: phy-mtk-tphy: make the ref clock optional
Sometimes the reference clock of USB3 PHY comes from oscillator
directly, and no need refer to a fixed-clock in DTS anymore
if make it optional.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions