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| author |   Jason Gunthorpe <jgg@nvidia.com> | 2020-07-27 11:44:36 -0300 |
|---|---|---|
| committer | Jason Gunthorpe <jgg@nvidia.com> | 2020-07-27 11:44:36 -0300 |
| commit | 79237743687178a56b282e6a8b9845ab0a54e598 (patch) | |
| tree | d85a63da78278f7d986545338eb0bdf6b7104790 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | RDMA/mlx5: Fix typo in enum name (diff) | |
| parent | RDMA/mlx5: Set mkey relaxed ordering by UMR with ConnectX-7 (diff) | |
| download | wireguard-linux-79237743687178a56b282e6a8b9845ab0a54e598.tar.xz wireguard-linux-79237743687178a56b282e6a8b9845ab0a54e598.zip | |
Merge branch 'mlx5_uar' into rdma.git /for-next
Meir Lichtinger says:
====================
ConnectX-7 supports setting relaxed ordering read/write mkey attribute by
UMR, indicated by new HCA capabilities, so extend mlx5_ib driver to
configure UMR control segment
====================
Based on the mlx5-next branch at
git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux
due to dependencies.
* branch 'mlx5_uar':
RDMA/mlx5: Set mkey relaxed ordering by UMR with ConnectX-7
RDMA/mlx5: Use MLX5_SET macro instead of local structure
RDMA/mlx5: ConnectX-7 new capabilities to set relaxed ordering by UMR
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