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| author |   Alex Bee <knaerzche@gmail.com> | 2023-08-29 22:37:23 +0200 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2023-10-04 23:23:38 +0200 |
| commit | 7e3be9ea299927e6d65242c247eca0a21bc26a58 (patch) | |
| tree | a4e855fc2bf95835a5884dfa90e60e673d8f82a7 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: rockchip: Fix i2c0 register address for RK3128 (diff) | |
| download | wireguard-linux-7e3be9ea299927e6d65242c247eca0a21bc26a58.tar.xz wireguard-linux-7e3be9ea299927e6d65242c247eca0a21bc26a58.zip | |
ARM: dts: rockchip: Add missing arm timer interrupt for RK3128
The Cortex-A7 timer has 4 interrupts.
Add the missing one.
Fixes: a0201bff6259 ("ARM: dts: rockchip: add rk3128 soc dtsi")
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20230829203721.281455-8-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions