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| author |   Ryan Wanner <Ryan.Wanner@microchip.com> | 2025-02-27 08:51:59 -0700 |
|---|---|---|
| committer |   Claudiu Beznea <claudiu.beznea@tuxon.dev> | 2025-03-02 17:38:54 +0200 |
| commit | 8bd10f002411c9ea947edc0af18ad81f789e28d5 (patch) | |
| tree | 9a8fe8a1c48de0235b0091af7af271ec63574b72 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: at91: pm: Add Backup mode for SAMA7D65 (diff) | |
| download | wireguard-linux-8bd10f002411c9ea947edc0af18ad81f789e28d5.tar.xz wireguard-linux-8bd10f002411c9ea947edc0af18ad81f789e28d5.zip | |
ARM: at91: pm: Enable ULP0/ULP1 for SAMA7D65
New clocks are saved to enable ULP0/ULP1 for SAMA7D65 because this SoC has a
total of 9 main clocks that need to be saved for ULP0/ULP1 mode.
Add mcks member to at91_pm_data, this will be used to determine
how many main clocks need to be saved. In the pm_mcks variable will also make
sure that no unnecessary clock settings are written during
mck_ps_restore.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/2ac0832f6ede17a5c111ede09b44b8a126e33e36.1740671156.git.Ryan.Wanner@microchip.com
[claudiu.beznea: adjusted the entry in pmc_infos[] array]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions