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| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2021-11-03 16:05:37 +0000 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2021-11-15 10:47:17 +0100 |
| commit | a0d2a2c6736c849463b424a7203f5e0e40949c03 (patch) | |
| tree | a6b9d6bf6a217719ea9380695696fe561f5c7849 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: renesas: rzg2l: Add missing kerneldoc for resets (diff) | |
| download | wireguard-linux-a0d2a2c6736c849463b424a7203f5e0e40949c03.tar.xz wireguard-linux-a0d2a2c6736c849463b424a7203f5e0e40949c03.zip | |
clk: renesas: r9a07g044: Add clock and reset entry for SCI1
Add clock and reset entry for SCI1 interface.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211103160537.32253-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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0 files changed, 0 insertions, 0 deletions