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| author |   Chris Zhong <zyw@rock-chips.com> | 2015-11-26 15:50:16 +0800 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2015-11-26 11:15:23 +0100 |
| commit | a2f4c560f18edd2ffe0f15d52ce2be55cff605d2 (patch) | |
| tree | 6c0500076dca05613569aa043fcea88eb7e8c981 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Merge branch 'v4.5-clk/clkids' into v4.5-clk/next (diff) | |
| download | wireguard-linux-a2f4c560f18edd2ffe0f15d52ce2be55cff605d2.tar.xz wireguard-linux-a2f4c560f18edd2ffe0f15d52ce2be55cff605d2.zip | |
clk: rockchip: add mipidsi clock on rk3288
sclk_mipidsi_24m is the gating of mipi dsi phy.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions