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| author |   Dmitry Osipenko <digetx@gmail.com> | 2020-03-19 22:36:47 +0300 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2020-06-22 13:54:57 +0200 |
| commit | adbcec8862cd7e3737e1488a98239f95dc45688f (patch) | |
| tree | 3cae99b2b610c36093c94495033952a9ca41d3f0 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | memory: tegra: Support derated timings on Tegra210 (diff) | |
| download | wireguard-linux-adbcec8862cd7e3737e1488a98239f95dc45688f.tar.xz wireguard-linux-adbcec8862cd7e3737e1488a98239f95dc45688f.zip | |
memory: tegra20-emc: Poll EMC-CaR handshake instead of waiting for interrupt
The memory clock-rate change could be running on a non-boot CPU, while the
boot CPU handles the EMC interrupt. This introduces an unnecessary latency
since boot CPU should handle the interrupt and then notify the sibling CPU
about clock-rate change completion. In some rare cases boot CPU could be
in uninterruptible state for a significant time (like in a case of KASAN +
NFS root), it could get to the point that completion timeouts before boot
CPU gets a chance to handle interrupt. The solution is to get rid of the
completion and replace it with interrupt-status polling.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions