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| author |   Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-09-02 23:32:14 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-09-03 12:00:23 +0200 |
| commit | baf5cb30fbd1c22f6aa03c081794c2ee0f5be4da (patch) | |
| tree | 838696ec1d299c082e4a16951a2e43e9af16efcb /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | MIPS: add missing MSACSR and upper MSA initialization (diff) | |
| download | wireguard-linux-baf5cb30fbd1c22f6aa03c081794c2ee0f5be4da.tar.xz wireguard-linux-baf5cb30fbd1c22f6aa03c081794c2ee0f5be4da.zip | |
MIPS: SNI: Fix SCSI interrupt
On RM400(a20r) machines ISA and SCSI interrupts share the same interrupt
line. Commit 49e6e07e3c80 ("MIPS: pass non-NULL dev_id on shared
request_irq()") accidently dropped the IRQF_SHARED bit, which breaks
registering SCSI interrupt. Put back IRQF_SHARED and add dev_id for
ISA interrupt.
Fixes: 49e6e07e3c80 ("MIPS: pass non-NULL dev_id on shared request_irq()")
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions