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| author |   Nickey Yang <nickey.yang@rock-chips.com> | 2017-09-18 17:05:37 +0800 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2017-09-19 19:25:10 +0200 |
| commit | bb4e6ff01ac356f82327d980e45fee8a65491328 (patch) | |
| tree | 47dceef62f8f8fd2ae3777a1b76674f04a99bcaa /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Revert "arm64: dts: rockchip: Add basic cpu frequencies for RK3368" (diff) | |
| download | wireguard-linux-bb4e6ff01ac356f82327d980e45fee8a65491328.tar.xz wireguard-linux-bb4e6ff01ac356f82327d980e45fee8a65491328.zip | |
arm64: dts: rockchip: Correct MIPI DPHY PLL clock on rk3399
There is a further gate in between the mipidphy reference clock and the
actual ref-clock input to the dsi host, making the clock hirarchy look like
clk_24m --> Gate11[14] --> clk_mipidphy_ref --> Gate21[0] --> clk_dphy_pll
Fix the clock reference so that the whole clock subtree gets enabled when
the dsi host needs it.
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
[amended commit message]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions