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| author |   Charlene Liu <Charlene.Liu@amd.com> | 2021-12-05 21:19:30 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2021-12-30 08:54:44 -0500 |
| commit | bf252ce1fa8ac68baee3f8525fc6453d278b619d (patch) | |
| tree | 39d11f541a514924bb8854252658b7d63f01e242 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/amdgpu: Check the memory can be accesssed by ttm_device_clear_dma_mappings. (diff) | |
| download | wireguard-linux-bf252ce1fa8ac68baee3f8525fc6453d278b619d.tar.xz wireguard-linux-bf252ce1fa8ac68baee3f8525fc6453d278b619d.zip | |
drm/amd/display: fix B0 TMDS deepcolor no dislay issue
[why]
B0 PHY C map to F, D map to G driver use logic instance, dmub does the
remap. Driver still need use the right PHY instance to access right HW.
[how]
use phyical instance when program PHY register.
[note]
could move resync_control programming to dmub next.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions