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| author |   Noah Abradjian <noah.abradjian@amd.com> | 2019-12-17 15:49:14 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-01-16 14:13:53 -0500 |
| commit | c1e3417558beda21fd41ed870ca16b36a69188d5 (patch) | |
| tree | 5172d8d42dcbff9cb2e2da91f28644aa6f3625e9 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/amd/display: DMCUB FW Changes to support PSR (diff) | |
| download | wireguard-linux-c1e3417558beda21fd41ed870ca16b36a69188d5.tar.xz wireguard-linux-c1e3417558beda21fd41ed870ca16b36a69188d5.zip | |
drm/amd/display: Indirect reg read macro with shift and mask
[Why]
Recent double buffering changes for dcn2 use IX_REG_READ.
However, this macro returns the full register value, with the need to
manually shift and mask it to retrieve field data.
[How]
Create new IX_REG_GET macro that handles shift and mask.
Use this for double buffering reads instead of IX_REG_READ.
Signed-off-by: Noah Abradjian <noah.abradjian@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions