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| author |   Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> | 2017-04-26 21:38:30 +1000 |
|---|---|---|
| committer |   Michael Ellerman <mpe@ellerman.id.au> | 2017-04-27 22:20:05 +1000 |
| commit | cf4f08bed876fbc50e64da92d2e1cfdf7653ddb2 (patch) | |
| tree | 40135afefaf8b0d3378f16296c89c4661d8ebfe7 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | powerpc/powernv: Fix oops on P9 DD1 in cause_ipi() (diff) | |
| download | wireguard-linux-cf4f08bed876fbc50e64da92d2e1cfdf7653ddb2.tar.xz wireguard-linux-cf4f08bed876fbc50e64da92d2e1cfdf7653ddb2.zip | |
powerpc/mm/radix: Optimise Page Walk Cache flush
Currently we implement flushing of the page walk cache (PWC) by calling
_tlbiel_pid() with a RIC (Radix Invalidation Control) value of 1 which says to
only flush the PWC.
But _tlbiel_pid() loops over each set (congruence class) of the TLB, which is
not necessary when we're just flushing the PWC.
In fact the set argument is ignored for a PWC flush, so essentially we're just
flushing the PWC 127 extra times for no benefit.
Fix it by adding tlbiel_pwc() which just does a single flush of the PWC.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
[mpe: Split out of combined patch, drop _ in name, rewrite change log]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to '')
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