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| author |   Dmitry Osipenko <digetx@gmail.com> | 2019-12-18 21:44:05 +0300 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2020-01-10 15:50:05 +0100 |
| commit | cf83a28f281fb3cce090e1b99d31b26baef9c13b (patch) | |
| tree | c6c43710dfe55a7f154c0df9faefc1384ad197a1 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: tegra: clk-dfll: Remove call to pm_runtime_irq_safe() (diff) | |
| download | wireguard-linux-cf83a28f281fb3cce090e1b99d31b26baef9c13b.tar.xz wireguard-linux-cf83a28f281fb3cce090e1b99d31b26baef9c13b.zip | |
clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation
UART clock is divided using divisor values from DLM/DLL registers when
enable-bit is unset in clk register and clk's divider configuration isn't
taken onto account in this case. This doesn't cause any problems, but
let's add a check for the divider's enable-bit state, for consistency.
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions