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author | 2015-12-22 10:12:42 -0800 | |
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committer | 2015-12-22 11:57:33 -0800 | |
commit | eaaa6fb53f2652760c1c512534fe3e71672a7d78 (patch) | |
tree | 7d132f3caec6b261f1d86df212962eaabcf59874 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | Merge branch 'clk-shmobile-for-v4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next (diff) | |
parent | clk: rockchip: only enter pll slow-mode directly before reboots on rk3288 (diff) | |
download | wireguard-linux-eaaa6fb53f2652760c1c512534fe3e71672a7d78.tar.xz wireguard-linux-eaaa6fb53f2652760c1c512534fe3e71672a7d78.zip |
Merge tag 'v4.5-rockchip-clk1_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Rockchip clock changes for 4.5 containing
- a new pll-type used on rk3036 and other Cortex-A7 socs
- new clock-trees for rk3036 and rk3228
- switch rk3288 plls to slow mode on reboot
- a bunch of new clock ids
- some more critical clocks
- wrong register offsets for the rk3368 cpuclks
- allowing more than 2 parents for the cpuclk
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