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| author |   Icenowy Zheng <icenowy@aosc.io> | 2020-01-03 22:35:03 -0800 |
|---|---|---|
| committer |   Maxime Ripard <maxime@cerno.tech> | 2020-01-04 09:17:06 +0100 |
| commit | ec97faff743b398e21f74a54c81333f3390093aa (patch) | |
| tree | ce53bd2eba2b2b584f3e0845d708717907e28b98 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: sunxi-ng: r40: Export MBUS clock (diff) | |
| download | wireguard-linux-ec97faff743b398e21f74a54c81333f3390093aa.tar.xz wireguard-linux-ec97faff743b398e21f74a54c81333f3390093aa.zip | |
clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock
The A64 PLL_CPU clock has the same instability if some factor changed
without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33,
H3.
Add the mux and pll notifiers for A64 CPU clock to workaround the
problem.
Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions