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| author |   Linus Walleij <linus.walleij@linaro.org> | 2018-02-06 10:35:38 +0100 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2018-02-07 09:08:40 +0100 |
| commit | eedd6033b4c88d559afd7c8ac8a76fefcd9834a6 (patch) | |
| tree | 2e276f18b5ce5ef45461abe4481318feb20367fd /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/pl111: Handle the Versatile RGB/BGR565 mode (diff) | |
| download | wireguard-linux-eedd6033b4c88d559afd7c8ac8a76fefcd9834a6.tar.xz wireguard-linux-eedd6033b4c88d559afd7c8ac8a76fefcd9834a6.zip | |
drm/pl111: Support variants with broken clock divider
The early Integrator CLCD synthesized in the Integrator CP and
IM-PD1 FPGAs are broken: their clock dividers do not work
properly. Support disabling the clock divider and drive the
clock directly from the parent under these circumstances.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20180206093540.8147-3-linus.walleij@linaro.org
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