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| author |   Kedareswara rao Appana <appana.durga.rao@xilinx.com> | 2016-04-07 10:59:45 +0530 |
|---|---|---|
| committer |   Vinod Koul <vinod.koul@intel.com> | 2016-05-12 11:58:58 +0530 |
| commit | 07b0e7d49cbcadebad9d3b986f3298e33286dea2 (patch) | |
| tree | cab6a2083edf13f0db17f8636d46f50a6ca10ef0 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Documentation: DT: vdma: update binding doc for AXI CDMA (diff) | |
| download | wireguard-linux-07b0e7d49cbcadebad9d3b986f3298e33286dea2.tar.xz wireguard-linux-07b0e7d49cbcadebad9d3b986f3298e33286dea2.zip | |
dmaengine: vdma: Add Support for Xilinx AXI Central Direct Memory Access Engine
This patch adds support for the AXI Central Direct Memory Access
(AXI CDMA) core to the existing vdma driver, AXI CDMA is a
soft Xilinx IP core that provides high-bandwidth
Direct Memory Access(DMA) between a memory-mapped
source address and a memory-mapped destination address.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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