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| author |   Pankaj Dubey <pankaj.dubey@samsung.com> | 2016-03-31 11:47:59 +0900 |
|---|---|---|
| committer |   Sylwester Nawrocki <s.nawrocki@samsung.com> | 2016-03-31 12:25:49 +0200 |
| commit | 27c0efedcf1be044dd638784189de816382f3f43 (patch) | |
| tree | fa26a9a02d0da8b66e7cb9d502d41779637badf2 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250 (diff) | |
| download | wireguard-linux-27c0efedcf1be044dd638784189de816382f3f43.tar.xz wireguard-linux-27c0efedcf1be044dd638784189de816382f3f43.zip | |
clk: samsung: exynos3250: Add UART2 clock
This patch add the UART2 clocks (mux, divider, gate) of Exynos3250 SoC.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions