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| author |   Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> | 2023-01-20 11:14:30 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2023-01-31 14:03:36 -0500 |
| commit | 4b0b4c17f5f6d4df40f2f79068909236858d61e0 (patch) | |
| tree | 4a182c341c9bea8716fe3bb933772b3706bd32fa /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/amd/display: Unassign does_plane_fit_in_mall function from dcn3.2 (diff) | |
| download | wireguard-linux-4b0b4c17f5f6d4df40f2f79068909236858d61e0.tar.xz wireguard-linux-4b0b4c17f5f6d4df40f2f79068909236858d61e0.zip | |
drm/amd/display: Reset DMUB mailbox SW state after HW reset
[Why]
Otherwise we can be out of sync with what's in the hardware, leading
to us rerunning every command that's presently in the ringbuffer.
[How]
Reset software state for the mailboxes in hw_reset callback.
This is already done as part of the mailbox init in hw_init, but we
do need to remember to reset the last cached wptr value as well here.
Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions