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| author |   Linus Torvalds <torvalds@linux-foundation.org> | 2023-12-08 09:03:54 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2023-12-08 09:03:54 -0800 |
| commit | 4df7c5fde316820286dfa6d203a1005d7fbe007d (patch) | |
| tree | c103a13c739c4c758909b3cad470c93152fe4e39 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Merge tag 'soc-fixes-6.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc (diff) | |
| parent | riscv: errata: andes: Probe for IOCP only once in boot stage (diff) | |
| download | wireguard-linux-4df7c5fde316820286dfa6d203a1005d7fbe007d.tar.xz wireguard-linux-4df7c5fde316820286dfa6d203a1005d7fbe007d.zip | |
Merge tag 'riscv-for-linus-6.7-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V fixes from Palmer Dabbelt:
- A pair of fixes to the new module load-time relocation code
- A fix for hwprobe overflowing on rv32
- A fix for to correctly decode C.SWSP and C.SDSP, which manifests in
misaligned access handling
- A fix for a boot-time shadow call stack initialization ordering issue
- A fix for Andes' errata probing, which was calling
riscv_noncoherent_supported() too late in the boot process and
triggering an oops
* tag 'riscv-for-linus-6.7-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: errata: andes: Probe for IOCP only once in boot stage
riscv: Fix SMP when shadow call stacks are enabled
dt-bindings: perf: riscv,pmu: drop unneeded quotes
riscv: fix misaligned access handling of C.SWSP and C.SDSP
RISC-V: hwprobe: Always use u64 for extension bits
Support rv32 ULEB128 test
riscv: Correct type casting in module loading
riscv: Safely remove entries from relocation list
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions