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| author |   Nava kishore Manne <nava.manne@xilinx.com> | 2019-01-25 13:16:54 +0530 |
|---|---|---|
| committer |   Michal Simek <michal.simek@xilinx.com> | 2019-01-29 14:08:40 +0100 |
| commit | 62f0d7dc3bae9f7ce2701d6c8cfd3d93130017af (patch) | |
| tree | 3c9a25263e65d7afb2f9d807a02700ee2cb932ab /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | dt-bindings: reset: Add bindings for ZynqMP reset driver (diff) | |
| download | wireguard-linux-62f0d7dc3bae9f7ce2701d6c8cfd3d93130017af.tar.xz wireguard-linux-62f0d7dc3bae9f7ce2701d6c8cfd3d93130017af.zip | |
reset: reset-zynqmp: Adding support for Xilinx zynqmp reset controller.
Add a reset controller driver for Xilinx Zynq UltraScale+ MPSoC.
The zynqmp reset-controller has the ability to reset lines
connected to different blocks and peripheral in the Soc.
Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions