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| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2023-08-24 09:30:06 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2023-11-27 11:00:02 +0100 |
| commit | ac2453d06c768b0604e231d6effabc1c405bd802 (patch) | |
| tree | 5f97c9bd206863c6bf1d273071ae59703f440032 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Linux 6.7-rc1 (diff) | |
| download | wireguard-linux-ac2453d06c768b0604e231d6effabc1c405bd802.tar.xz wireguard-linux-ac2453d06c768b0604e231d6effabc1c405bd802.zip | |
arm64: defconfig: Enable Renesas VersaClock 3 clock generator config
Enable the config for the Renesas VersaClock 3 programmable clock
generator, as it is populated on RZ/{G2L,G2LC} and RZ/V2L SMARC EVKs.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230824083006.88944-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions